Search results for "Nuclear electronics"
showing 10 items of 29 documents
Commissioning Experience with the ATLAS Level-1 Calorimeter Trigger System
2007
The ATLAS Level-1 Calorimeter Trigger is one of the main elements of the first stage of event selection for the ATLAS experiment at the LHC. The input stage consists of a mixed analogue/digital component taking trigger sums from the ATLAS calorimeters. The trigger logic is performed in a digital, pipelined system with several stages of processing, largely based on FPGAs, which perform programmable algorithms in parallel with a fixed latency to process about 300 Gbyte/s of input data. The real-time output consists of counts of different types of physics objects and energy sums. The production of final modules started in 2006, and installation of these modules and the necessary infrastructure…
The sROD demonstrator for the ATLAS Tile Calorimeter Upgrade
2012
This work presents the early design of the super Read-Out Driver (sROD) demonstrator board for the Tile Calorimeter Demonstrator project. This project aims to test the new readout electronics architecture for the Phase 2 Upgrade of the ATLAS Tile Calorimeter, replacing the front-end electronics of one complete drawer with the new electronics during the Long Shutdown 2013, in order to evaluate its performance. The sROD demonstrator board will receive and process data from 48 channels. Moreover the sROD demonstrator board will send preprocessed data to the present trigger system, and will transmit trigger control and timing information (TTC) and Detector Control System (DCS) commands to the f…
The Optical Multiplexer Board for the ATLAS Hadronic Tile Calorimeter
2007
This paper presents the architecture and the status of the optical multiplexer board (OMB) for the ATLAS/LHC tile hadronic calorimeter (TileCal). This board will analyze the front-end data CRC to prevent bit and burst errors produced by radiation. Besides, due to its position within the data acquisition chain it will be used to emulate front-end data for tests. The first two prototypes of the final OMB 9U version have been produced at CERN. Detailed design issues and manufacturing features of these prototypes are described. These prototypes are being validated while firmware developments are being implemented in the programmable devices of the board.
Fast and compact data acquisition for gas-filled detectors with delay line
2004
This article describes the functionality, implementation and performance of a PCI data acquisition board that can be used in conjunction with gas-filled detectors with delay line readout. The board combines a large on-board 256-MByte histogramming memory with a maximum 10-MHz count rate in continuous operation and integrates the time frame generation, histogram building and buffering functionalities in a single PCI board, resulting in a fast, compact and cost-effective data acquisition solution for the Spanish beamline BM16 at ESRF.
The Argo YBJ daq system and the GRID based data transfer
2008
The Argo-YBJ experiment has now reached itsfinal design configuration. The detector system consists of a fullcoverage array (about 5800 square meters) of Resistive PlateChambers (RPCs). The throughput depends on the trigger rateand threshold. The DAQ system must be able to sustain a max-imum transfer rate of the order of 15 MB/s and a high peakdata flow. Data are read out using a typical front-end acquisitionchain built around a custom bus. Specialized electronics have beendesigned and dedicated software has been written to perform thistask. Data are sent to the online farm through a switch exploitinga gigabit ethernet protocol. A solution to transfer data from theYBJ laboratory to the labo…
Overview of the high-level trigger electron and photon selection for the ATLAS experiment at the LHC
2005
texte intégral : http://cdsweb.cern.ch/record/846438; The ATLAS experiment at the Large Hadron Collider (LHC) will face the challenge of efficiently selecting interesting candidate events in$pp$collisions at 14 TeV center-of-mass energy, whilst rejecting the enormous number of background events. The High-Level Trigger (HLT$=$second level trigger and Event Filter), which is a software based trigger will need to reduce the level-1 output rate of$approx75$kHz to$approx200$Hz written out to mass storage. In this talk an overview of the current physics and system performance of the HLT selection for electrons and photons is given. The performance has been evaluated using Monte Carlo simulations …
Evaluation of a commercial APD array (Avalanche PhotoDiode) for a readout detector in a hadrontherapy beam characterization application
2010
The aim of the present work is the characterization of the S8898–128–02 Avalanche PhotoDiode array (APDs) from Hamamatsu Photonics. This work includes the implementation of a readout system as well as electronic noise estimation in APDs under several conditions varying integration times and clock frequencies.
MALTA: a CMOS pixel sensor with asynchronous readout for the ATLAS High-Luminosity upgrade
2018
Radiation hard silicon sensors are required for the upgrade of the ATLAS tracking detector for the High- Luminosity Large Hadron Collider (HL-LHC) at CERN. A process modification in a standard 0.18 μm CMOS imaging technology combines small, low-capacitance electrodes (∼2 fF for the sensor) with a fully depleted active sensor volume. This results in a radiation hardness promising to meet the requirements of the ATLAS ITk outer pixel layers (1.5 × 1015 neq /cm2 ), and allows to achieve a high signal-to-noise ratio and fast signal response, as required by the HL-LHC 25 ns bunch crossing structure. The radiation hardness of the charge collection to Non-Ionizing Energy Loss (NIEL) has been previ…
Optimal filtering algorithm implementation in FPGAs for the ATLAS TileCal Read-Out drivers
2011
TileCal is the hadronic calorimeter of the ATLAS experiment in the LHC (CERN). Its Read-Out Drivers (RODs) process, in real time, the digitized information coming from the front-end electronics and send it to the Read-Out System. Data processing in the ROD boards is performed in Processing Unit Mezzanine Cards that use commercial DSPs to run the Optimal Filtering (OF) algorithms.
The ATLAS TileCal read-out drivers signal reconstruction
2009
TileCal is the hadronic calorimeter of the ATLAS experiment at the LHC collider at CERN. The Read-Out Drivers (ROD) are the core of the off-detector electronics. The main components of the RODs are the Digital Signal Processor (DSP) placed on the Processing Unit (PU) dautherboards. This paper describes the DSP code and its performance with calibration and real data. The code is divided into two different parts: the first part contains the core functionalities and the second one the reconstruction algorithms. The core acts as an operating system and it controls the configuration, the data reception, transmission, online monitoring and the synchronization between front-end data and the Trigge…